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The digital processing unit (DPU) includes a burst-mode processor (BMP), digital receiver transmit (DRT), and a programmable interface between the analog processing unit (APU).
- Interface to APU through serial link
- Interface composed of two DAIF blocks on the DPU and ADIF on the APU
- DPU includes:
- BMP (burst-mode processor) – Fully controlled by software, the BMP is responsible for:
- Support bit and slot formatting
- Support error control coding and decoding
- Generation of timing references
- Control RF timing
- Control serial interface for the synthesizer
- Control serial peripheral interface for RF19
- Software control
- DRT (digital receive transmit)
- Two full duplex voice channels
- HW decimation and interpolation with 32 KHz (DECT/WDCT) or 40 KHz (BT) sampling rate
- Processor interface at 32KHz (DECT/WDCT) or 40KHz sampling rate
- Timing synchronization to speech frame interrupt
- DAIF – Programmable interface between the DPU and APU, carries power, reset, RF control and data signals as well as the clock from the crystal oscillator
- CGU (PLL) – Clog generation units
- Generation and distribution of high frequency clocks
- WDRU – Watchdog and reset unit
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Product Graphics
Block Diagram
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