S M A R T C O R E S P U B L I S H E D A R T I C L E S
DRAM-ASIC based Design for Low Power Systems
Farzad Zarrinfar
Samsung Semiconductor, Inc.
3655 North First Street
San Jose, CA 95134-1713
(408) 954-7027
Email : fzarrin@ssi.samsung.com
Abstract:
This paper discusses the benefits of embedded DRAM-ASIC technology using 3.3 Volt power supply, including enabling increased performance (bandwidth), minimizing power consumption and noise, minimizing design pins as well system’s form factor, increasing reliability, and minimizing cost of ownership for systems.
This paper also elaborates on the benefits of major cores and building blocks in highly integrated and power efficient "Digital Cellular Phone". These major cores and building blocks include RF / IF interface using mixed-signal technology, 32-bit RISC (ARM7TDMI) based processing and DSP processor (OakDSPCore), video sub-system and power management unit in a System-On-A-Chip. This article also explains the impact of DRAM-ASIC technology in lowering cost and enhancing the battery life of portable devices.
The organization of this paper is as follows: discussion of the "Demand For High Bandwidth and low power consumption" ; description of an architectural example, (Digital Cellular Phone); depiction of blocks such as RF/IF, RISC/DSP Processors, Video Sub-system, Memory, Power Management; discussion of the optimum test methodologies for portable system-on-a-chip design such as Digital Cellular Phone; and finally, a conclusion is provided.
Demand For High Bandwidth and low power consumption:
Requirement for higher performance sub-systems involving signal processing and video applications are continuously increasing. Instruction execution has been growing dramatically with increasing processor performance. In contrast, the bandwidth capabilities of DRAMs have been growing at a much slower rate.
This is causing a performance gap in modern systems, Figure 1, which is creating a system bottleneck. Another requirement for portable systems is that they operate with minimum power consumption to minimize battery size and increase battery life. By embedding processors and DRAMs in a single chip and utilizing wide internal busses, high bandwidth can be accomplished; additionally, by embedding processors and DRAMs in a single chip and utilizing wide internal busses will minimize power dissipation. This architectural implementation requires technology innovation, which is done by "Merged DRAM Logic (MDL) technology of Samsung. This DRAM-ASIC technology is extremely attractive in variety of portable applications such as Digital Cellular Phones.
Figure 1: MDL technology is the enabling solution for closing the performance gap
Digital Cellular Phone:
Modern Digital Cellular Phones, in addition to typical phone capability, include functions such as video [2,3], modem, wireless internet/intranet to allow web browsing, and two-way wireless messaging providing functionality of alphanumeric pagers.
Digital Cellular Phone contains a RF/IF analog portion. This portion is followed by digital baseband segment which includes Digital Signal Processor (DSP), and 32-bit RISC microprocessor in the same ASIC which decodes, decompresses and puts the incoming signal into a format that the user can use, Figure 2. Modern cellular phones are integrating video as an option. This integration can be achieved with 0.5um CMOS technology, which also allow for addition of DRAMs, SRAMs, ROMs, Datapaths, mixed-signal functions such as A-D/D-A converters and Phase-Locked Loops (PLL). For forward migration and cost optimization, 0.5um feature size, is being followed with 0.35um, 0.25um, and 0.18um technologies.
Figure 2:System Architecture For Digital Cellular Phone
RF/IF Section:
The Radio Frequency (RF)/ Intermediate frequency (IF) front end is related to the transmission and reception of information through the air. This RF subsystem is typically implemented using discrete devices and either adds or removes the carrier frequencies from the information being transferred through the air. These devices include "Power Amp", "Driver", "Up Converter", ‘Band Pass Filter (BPF)", "Automatic Gain Control (AGC) Amp", "TCXO", "Diplex Filter", "Low Noise Amplifier (LNA), "RF Filter", "Mixer", "IF Filter", "Down Converter", and "Low Pass Filter", Figure 2. For example, the incoming signal from the antenna is down converted from high RF frequency to its baseband using mixing stages. In communication access schemes such as Code Division Multiple Access, (CDMA), the RF section is designed to work in the 900MHZ band.
In the first conversion stage, the RF input signal is "mixed" with its sine and cosine elements, using 1GHz reference signal generated by a local oscillator, ( I )/( Q ) signals are generated. In a digital receiver system using IF sampling, the first-stage applies to signals; one in-phase with the receiver RF signal ( I ), and the other consisting of quadrature component (phase-shifted elements) of the RF signal ( Q ) provided by local oscillator. The result is sum and difference frequencies at 1.9GHz and 100 MHz. The bandpass filter removes the 1.9 GHz product, leaving the 100 MHz IF signal. This is then down converted and filtered. The spectrum of interest is from dc to +5MHz.
The following are brief descriptions of RF/IF building blocks:
TCXO is the monolithic, low-power, high-performance dual frequency synthesizer. This block is typically fabricated in BiCMOS technology and features ‘Fractional-N’ division. The ‘Fractional-N’ divider reduces the division ratio, allowing for a lower noise floor and faster channel switching. TCXO is being controlled by ARM7TDMI and adjust the response of the first IF stage.
The upconverter (BPSK modulator) is typically fabricated by BiCMOS technology and its characteristics include 10.5 dB SSB noise figure in conjunction with a +.05dB typical conversion gain and it is able to transmit output signals in applications that require large dynamic ranges. In general, the baseband processor enforces the modulation scheme for the phone system. The two most common types of modulation in use today are GMSK )Gaussian Minimum Shift Keying) and p/4 DQPSK (p /4 Shifted Differentail Quadrature Phase Shift Keying).
The reciver front end is designed to amplify and down-convert RF signals while providing approximately 9dB of gain control range. The IF output is digitally controllable. The receiver’s down converter is typically designed with buffered LO output which can be disabled to conserve current consumption from a single 3.3 V power supply.
The AGC amplifiers (BiCMOS) are used in receive and transmit sections. They typically amplify IF signals while providing either 90dB or 84dB of gain control range.
The driver amplifier is typically fabricated in GaAs and features a minimum gain control range of 15dB, a maximum noise figure of 4.5dB and it typically includes all of its input and output matching components on-chip.
The power amplifier is designed for increased power efficiency in handsets. The power amplifier is typically fabricated with GaAs technology and could require off-chip output matching and associated bias circuitry.
The Low Noise Amplifier (LNA) is the RF front end, which interface with mixer. LNA is typically manufactured with GaAs technology.
The RF/IF section also includes D/A converters. These are used to control the output power of transmission.
RISC Processor:
A RISC processor such as ARM7TDMI from Advanced RISC Machines, which is supported by Samsung, provides control for all the subsystems in the phone. Phone operation data from the basestation as well as user inputs are routed through this RISC processor. When a call is being set up, the microprocessor receives information on which channels will be used and the microprocessor instructs the RF/IF subsystem which frequencies to use. The user inputs through the keypads are analyzed by ARM7TDMI and requested operation is performed. Using RISC processor, most of instructions execute in a single cycle. For example, using 0.5um CMOS technology, ARM7TDMI can operate from DC to over 40 MHz. This area-optimized processor will enable designers to achieve lowest form factor for their systems. ARM7TDMI includes three-stage pipeline architecture, which enable systems to execute an instruction every cycle. This 32/16-bit instruction set processor includes 32 bit ALU, barrel shifter, and address bus. This is enhanced with 4GB of address range. For modern digital cellular phone, depending to features, 1 to 8 M bytes of memory is required. The ARM7TDMI consumes approximately 1.0 ma/MHz using 3.3V power supply.
This processor also includes JTAG testability port. This port is used for board level testing, debug support and embedded In Circuit Emulation (ICE) for setting hardware breakpoint tracing program execution.
For supporting system-on-a-Chip level designs [1], various deliverables such as Verilog model, Native VHDL-IEEE 1076 model, Synthesis model, C/C++ models, Assemblers, symbolic debugger, Real Time Operating System (RTOS), ARM Software Development Tool, Development Board, Functional/Scan ATPG Test Vectors, stand alone parts and ICE software is available. Samsung, ARM, and 3rd party tool suppliers can each provide some these deliverables.
DSP Processor:
One of the key components used in digital cellular phone is the digital signal processor (DSP), a specialized microprocessor that excels at performing multiply-and-add in the form of A=D+B*C. These are used to manipulate and process voice, video and data signals. The OakDSPCore, which is supported by Samsung, can execute with 25ns clock cycle at 5.0Volts and 30ns cycle time at 3.3 Volts. The OakDSPCore consumes approximately 0.52 mA/MHz using 3.3V power supply.
This DSP processor features a single cycle instruction set, 16 bit fixed-point core, with 16*16 bit multiplier, single cycle multiply/accumulate instructions, 32 bit ALU and includes four 36 bit accumulate. OakDSPCore is used extensively in base stations to perform channel coding, echo cancellation, equalization and encryption on the transmitted signal. The channel coding function involves packing transmissions with error correction information so that they are less susceptible electromagnetic interference as well as interference from buildings, mountains and other structures. OakDSPCore is also used for data compression, decompression, and digital filtering applications that handle large data sets from processor to DRAM.
Adaptive equalization is used in base station to eliminate the problems that can occur when a signal transmitted by a cell phone takes multiple paths to the base station antenna. This situation results in multiple versions of a transmission, each with different signal strength, arriving at the base station at different times. If signals are not processed properly, transmitted signal will not be suitable for conversation.
For digital wireless system, DSP engine is also used for encryption, which provides security during transmissions and prevents eavesdropping of calls. DSP engine is also used for speech compression and decompression. This will provide more capacity than analog systems using the same amount of available spectrum. Two compression methods in use today are VSELP (Vector Sum Exited Linear Predictive) and RPELTP (Regular Pulse Excitation Long Term Predictive).
DSP engine is also used for channel coding which enforces proper channel access. This channel coding is designed specifically for selected protocol, which the phone is designed to operate with. The two most common protocols in use today are Code Division Multiple Access (CDMA) and Time Division Multiple Access (TDMA).
Modem function can also be implemented in cellular phone, using OakDSPCore. Using modem blocks, voice and data together can be transmitted using digital cellular phone. Standards such as V.34 and V.32 are frequently used. These standards are implemented and using high performance DSP engine such as OakDSPCore. V.32 facilitates synchronous, full duplex transmission over two wire switched circuits at 9600 bps, with a fallback speed of 4800 bps for deteriorating transmission condition. V.32bis modems operate at 14.4 Kbps with fallback rates of 12K, 9.6K, 7.2K, and 4.8K bps. The V.32bis standard eliminates the need for users to reestablish connections to regain higher-speed operations, a situation that occurs when modems have to lower their transmission speeds to adjust to deteriorating transmission condition. On the other hand, V.34 supports data rates up to 28,800 bps. Proliferation of V.32 and V.34 modems will also drive new applications, such as simultaneous remote access to the corporate PBX and LAN for telecomputing.
For supporting system-on-a-Chip level designs [1], varies deliverables such as Verilog model, Synthesis model, C-compiler, Assemblers, Linker, symbolic debugger, Floor Planning, Functional Test Vectors, stand alone parts, and ICE software is available. Samsung, ParthusCeva, and 3rd party tool suppliers can each provide some these deliverables.
Audio CODEC:
Audio CODECs are used to provides high quality voice transmission in telephony systems.
The audio CODEC could use Sigma-Delta processing technology which contain multiple A-to-D and D-to-A converters. This type of CODEC would be based on Sigma-Delta modulation techniques. Using this technology, sample rate range of 4KHz to 48KHz could be supported.
Video Sub-system:
A highly optimized processor such as ARM7TDMI can be used to control video sub-system. This video section is an integrated part of digital cellular phone for providing multimedia conferencing and Internet access. Also features such as video scaling and full-speed video playback is possible using display controller and using up to 4MB of frame buffer SDRAM. This SDRAM is implemented with MDL technology. This newly developed, unified process technology is involved with Merged DRAM and Logic technology (MDL) innovation to maximize the performance and reduce power consumption of this sub-system.
Memory:
Memory is used as a storage location for the phone’s Electrical Serial Number (ESN). Memory also is used as a storage location for subsystem operation instruction and maintaining frequently used numbers. In phones that have massaging, user memory may be accessed by the local-loop phone system to store a message. For Video applications, also approximately 8 M byte of DRAM is required. This can be implemented using Samsung’s sub-half micron technology. Flash memory is also used so that operating systems can be updated without having to replace IC’s.
Power Managent:
Price of ASIC package increases with increased power dissipation characterisitc od ASIC package.
P max = (Tj-Ta)q ja
Where,
Pmax = Maximum power dissipation
Tj = Maximum allowable junction temperature
Ta = Ambient temperature
q ja = Junction-to-ambient thermal resistance
Figure3: Maximum Power Dissipation and Normalized comparison of various packages
As Figure 3 Illustrates, in respect with cost of ownership for specific package, designers attempt to minimize the power dissipation of their required package. Using on-chip DRAM, implementing active power management, and implement functionality with lowest operating voltage, would enable designers to minimize ASIC’s power dissipation.
The on-chip DRAM reduces the power consumption of embedded system by eliminating drive requirement for I/O pins, which occur in traditional communication between microprocessor chip and DRAM chip. This minimization in power consumption could be as high as 60%[…]. Designers are also continuously performing trade-off analysis between area, power consumption, performance, and testability of their ASICs.
An active power management is an essential part of digital cellular phone to allow over 16 hours of "Standby Time" and several hours "Talk Time". The system’s power consumption can be reduced in real-time when cores are clocked at lower frequency, when ever is possible. For example, Palette DAC shutdown by microprocessor is used to shutdown unused further conserve battery life. Using ASIC’s embedded A/D converters and ARM7TDMI, system’s battery level can be easily monitored.
Test Methodology for DRAM-ASIC designs:
Innovative process in DRAM-ASIC opens a suite of challenges for simulation, memory compilation, timing analysis, power analysis and test generation. In Samsung, internal development as well as partnership are addressing these with leading-edge EDA companies. DRAM testing is an example of internal development. This comprehensive test solution will minimize ASIC designer’s effort for test generation, which manifest itself to shorter time to market.
In DRAM-ASICs, scan path and functional vectors are used for testing logic part which is implemented by cell base technology. DRAM section is tested by direct access to DRAM as well as built In Self-Test (BIST). Direct access is essential for fault localization, memory repair, testing repaired DRAM as well as testing critical AC parameters. Some DRAM specific tests such as "refresh time" test will also be performed during direct access test. This is complemented with BIST testing which is being performed at-speed. The embedded BIST logic will test the embedded DRAM core at 100 MHz for functionality and AC parameters at package level. DRAM-ASICs are also tested for DC parameters such as open/short, standby current, input/output leakage, voltage reference and substrate bias test.
Samsung, the leading producer of memory products, has found Column March 14N pattern as the most optimum test pattern for testing embedded DRAM blocks. These test methodologies support EDO, Fast Page, SDRAM, and SGRAM architectures as embedded DRAM blocks.
Conclusion:
DRAM-ASIC technology, is an ideal solution for high performance and low power System-On-A-Chip applications. The availability of embedded DRAM-ASIC and complex cores provide the most comprehensive suite of design solutions for practical partitioning and design of wireless systems such as "Digital Cellular Phone".
Acknowledgment:
The author is grateful to Lori Westenberger, S.H. Hong, Ajay Lalwani, Zafar Malik, Susan Cain, and Susan Zarrinfar for their many valuable comments.
References:
[1] F.Zarrinfar, "Sign-off Methodology For System-on-a-Chip", Proceeding of the 1996 Electronic Design Automation & Test Conference.
[2] F.Zarrinfar, "An Effective Emulation Methodology for System-on-a-Chip", Proceeding of the 1995 Electronic Design Automation & Test Conference.
[3] L. Hanzo, "A Low-Rate Multi-Level Voice/Video Transceiver for Personal Communications", An International Journal of Wireless Personal Communications, Volume 2, 1995.